Combined handling, testing, and sorting machine for integrated circuits



FIG. 1 is a perspective view of a combined handling, testing and sorting machine for integrated circuits showing my new designs;

FIG. 2 is a side elevational view taken from the right side of FIG. 1;

FIG. 3 is a side elevational view taken from the left side of FIG. 1;

FIG. 4 is a top plan view thereof, the bottom being unornamented; and

FIG. 5 is a rear elevational view thereof. 

The ornamental design for a combined handling, testing, and sorting machine for integrated circuits, substantially as shown and described. 